The present invention generally relates to optical masks and methods of producing the same, and more particularly to an optical mask which uses a phase shift exposure to improve the resolution, and a method of producing such an optical mask.
There are demands to increase the operating speed of large scale integrated circuits (LSIs), such as a memory device having a large memory capacity, and to improve the integration density of the LSIs. For this reason, there are demands to realize a fine photolithography technique.
As one prominent means of satisfying the above demands, there is a phase shift exposure technique which employs an optical mask using a phase shift, and a coherent light source which emits an exposure light having a wavelength which is as short as possible. The optical mask using the phase shift will hereinafter be referred to as a phase shift optical mask.
FIG.1 shows in cross section an example of a conventional phase shift optical mask. The phase shift optical mask shown in FIG.1 includes a glass substrate 11, a chromium (Cr) layer 12 and a silicon dioxide (SiO.sub.2) layer 13 which forms a phase shift part.
When producing this phase shift optical mask, the Cr light blocking layer 12 which blocks the exposure light is formed on the entire surface of the glass substrate 11 which is transparent with respect to the exposure light. Then, the SiO.sub.2 layer 13 which is also transparent with respect to the exposure light is formed on the Cr light blocking layer 12 to a thickness such that the phase of the exposure light is shifted by 180.degree..
Thereafter, a resist layer (not shown) with an opening is formed on the SiO.sub.2 layer 13 and the SiO.sub.2 layer 13 is etched using a photolithography technique so as to form an opening 14. This opening 14 has the size and shape of a predetermined main light transmitting part. Next, the SiO.sub.2 layer 13 is used as a mask and the Cr light blocking layer 12 which is within the opening 14 is subjected to an isotropic etching. As a result, the SiO.sub.2 layer 13 overhangs above the Cr light blocking layer 12 to form the phase shift part.
However, when the phase shift optical mask is subjected to a cleaning or brushing during the production stage or in a stage before the phase shift optical mask is actually used, there are problems in that the SiO.sub.2 layer 13 easily separates from the Cr light blocking layer 12 and that a part of the SiO.sub.2 layer 13 may become damaged and come off the phase shift optical mask.
On the other hand, when producing the phase shift optical mask by the conventional technology, there is a limit to the precision with which the patterns may be formed by the photolithography technique. For this reason, there a problem in that it is extremely difficult to form, in the SiO.sub.2 layer 13 an opening which has a desired size and shape. In addition, when subjecting the Cr light blocking layer 12 to a side etching, there is also a problem in that it is difficult to control the side etching quantity.
In other words, the light intensity distribution of the exposure light transmitted through the phase shift optical mask is dependent on a width L2 of the SiO.sub.2 layer 13 overhanging the Cr light blocking layer 12, as will be described hereunder. FIG.2A shows the light intensity distribution of the exposure light transmitted through the phase shift optical mask shown in FIG. 1 when L1=0.50 .mu.m and L2=0.15 .mu.m, where L1 denotes the width of the Cr light blocking layer 12. Similarly, FIG. 2B shows the light intensity distribution for a case where L1=0.5 .mu.m and L2=0.20 .mu.m, and FIG. 2C shows the light intensity distribution for a case where L1=0.50 .mu.m and L2=0.10 .mu.m. In other words, FIGS. 2B and 2C respectively show the distributions for the cases where the width L2 of the SiO.sub.2 layer (phase shift part) 13 is varied by .+-.0.05 .mu.m on the wafer.
In FIGS. 2A through 2C, a solid line indicates the distribution at a defocus of 0.000 .mu.m, a dashed line indicates the distribution at a defocus of 0.300 .mu.m, a fine dotted line indicates the distribution at a defocus of 0.600 .mu.m, a one-dot chain line indicate the distribution at a defocus of 0.900 .mu.m, and a two-dot chain line indicates the distribution at a defocus of 1.200 .mu.m. Further, the wavelength .lambda. of the exposure light is 0.365 .mu.m, the numerical aperture (NA) of an exposure lens is 0.54, and the coherency factor .sigma. is 0.30.
In the case shown in FIG. 2B, the resist layer on the wafer is exposed by the peaks appearing on both sides of the distribution, and more of the resist layer is developed when compared to the case shown in FIG. 2A. The width of the opening in the resist layer after the developing step is approximately the distance in the distribution at the light intensity of 0.3. In the case shown in FIG. 2B, the width of the opening in the resist layer is 0.35 .mu.m which is slightly smaller than the width of 0.36 .mu.m which is obtained in the case shown in FIG. 2A. On the other hand, in the case shown in FIG. 2C, the width of the opening in the resist layer is 0.39 .mu.m which is considerably greater than the 0.36 .mu.m obtained in the case shown in FIG. 2A. Therefore, it can be seen that the deviation of .+-.0.05 .mu.m of the width L2 exceeds the tolerable deviation range.
The side etching of the Cr layer 12 lacks stability, and the side etching rate is greatly dependent on the conditions of the preprocessing, which is carried out before the side etching, and also the etching pattern or etching area. Particularly, the side etching rate varies from 0.03 .mu.m/min to 0.07 .mu.m/min, and under this variation range, an error of 0.05 .mu.m appears on the wafer at 3.sigma.. Therefore, as described above, it is extremely difficult to control the width L2 of the SiO.sub.2 layer 13 to a desired value which is within a tolerable range when the side etching of the Cr layer 12 is required.